<
From version < 23.1 >
edited by Edwin Chen
on 2022/11/16 15:27
To version < 20.1 >
edited by Bei Jinggeng
on 2022/11/15 10:27
>
Change comment: There is no comment for this version

Summary

Details

Page properties
Author
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1 -XWiki.Edwin
1 +XWiki.Bei
Content
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43 43  |(% style="width:179px" %)AT+DI2TODO2=2 |(% style="width:177px" %)AT+DI2TODO2=2
44 44  |(% style="width:179px" %)AT+DI2TORO2=2|(% style="width:177px" %)AT+DI2TORO2=2
45 45  
46 +
46 46  === 2.2.3 Serial port display ===
47 47  
48 48  
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402 402  
403 403  **Command:**
404 404  
405 -**AT+TRIG2=2,50,60**  Once there is falling edge or rising edge on DI2 of LT1, LT1 will transmit trigger to LT2 and LT2 can sync the status of RO/DO. After power off, power on, LT1 will send trigger without falling/rising edge, so the DI changes during power off will be sync as well.
406 +**AT+TRIG2=2,50,60**  Once there is falling edge or rising edge on DI2 of LT1, LT1 will transmit trigger to LT2 and LT2 can sync the status of RO/DO.
406 406  
407 407  
408 408  === 2.3.2 RO/DO is configured in the receiver LT (LT2)(Since firmware 1.3) ===
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481 481  
482 482  When DI2 is enabled as sleep pin, a falling trigger (with 500ms pulse) will set LT into sleep mode. A raising trigger will wake up it again.
483 483  
484 -In sleep mode, DORO will keep its initial state if AT+DOROSAVE=2, otherwise DORO will be in OFF state
485 485  
486 -
487 487  == 2.4 Data Format ==
488 488  
489 489  
... ... @@ -492,7 +492,7 @@
492 492  )))
493 493  
494 494  (((
495 -(% style="color:blue" %)**Payload:Payload triggered by TDC or DI**
494 +(% style="color:blue" %)**Payload:**
496 496  )))
497 497  
498 498  (% border="1" style="background-color:#f7faff; color:black; width:825px" %)
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655 655  
656 656  (((
657 657  (((
658 -(% style="color:#037691" %)**The fourth byte**(%%)**:**  the high four bits are 1 to represent DOI1, and the low four bits are the level of DOI2 when the interrupt is triggered.
657 +(% style="color:#037691" %)**The fourth byte**(%%)**:**  the high four bits are 1 to represent DOI1, and the low four bits are the level of DOI1 when the interrupt is triggered.
659 659  )))
660 660  )))
661 661  
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